View IMX29F002TQI-70_8724165.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the mx29f002t/b is a 2-mega bit flash memory organ- ized as 256k bytes of 8 bits only. mxic's flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. the mx29f002t/b is packaged in 32-pin pdip,plcc and 32-pin tsop(i). it is designed to be reprogrammed and erased in-system or in- standard eprom programmers. the standard mx29f002t/b offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the mx29f002t/b has separate chip enable (ce) and output enable (oe) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the mx29f002t/b uses a command register to manage this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maximum eprom compatibility. features ? 262,144x 8 only fast access time: 55/70/90/120ns low power consumption - 30ma maximum active current(5mhz) - 1ua typical standby current programming and erasing voltage 5v 10% command register architecture - byte programming (7us typical) - sector erase (16k-byte x1, 8k-byte x 2, 32k-byte x1, and 64k-byte x 3) auto erase (chip & sector) and auto program - automatically erase any combination of sectors or the whole chip with erase suspend capability. - automatically programs and verifies data at specified address erase suspend/erase resume - suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation. status reply 1 - data polling & toggle bit for detection of program and erase cycle completion. sector protection - hardware method to disable any combination of sectors from program or erase operations - sector protect/unprotect for 5v only system or 5v/12v system 100,000 minimum erase/program cycles latch-up protected to 100ma from -1 to vcc+1v boot code sector architecture - t = top boot sector - b = bottom boot sector hardware reset pin(only for 29f002t/b) - resets internal state machine to read mode low vcc write inhibit is equal to or less than 3.2v package type: - 32-pin pdip - 32-pin plcc - 32-pin tsop (type 1) 20 years data retention p/n: pm0547 rev. 1.5, mar. 28, 2005 mxic's flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx29f002t/b uses a 5.0v 10% vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. mx29f002/002n t/b 2m-bit [256k x 8] cmos flash memory
2 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b pin configurations 32 pdip sector structure 32 plcc 32 tsop (type 1) (normal type) pin description symbol pin name a0~a17 address input q0~q7 data input/output ce chip enable input we write enable input reset hardware reset pin/sector protect unlock oe output enable input vcc power supply pin (+5v) gnd ground pin mx29f002t sector architecture mx29f002b sector architecture mx29f002t/b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 reset a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc we a17 a14 a13 a8 a9 a11 oe a10 ce q7 q6 q5 q4 q3 nc on mx29f002nt/b a11 a9 a8 a13 a14 a17 we vcc reset a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a10 ce q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx29f002t/b (nc on mx29f002nt/b) 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe a10 ce q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 vss q3 q4 q5 q6 a12 a15 a16 reset vcc we a17 mx29f002t/b nc on mx29f002nt/b 16 k-byte 8 k-byte 8 k-byte 32 k-byte 00000h 3ffffh (boot sector) 64 k-byte 64 k-byte 64 k-byte 3bfffh 39fffh 37fffh 2ffffh 1ffffh 0ffffh a17~a0 16 k-byte 8 k-byte 8 k-byte 32 k-byte 00000h (boot sector) 64 k-byte 64 k-byte 64 k-byte 3ffffh 2ffffh 1ffffh 07fffh 05fffh 03fffh 0ffffh a17~a0
3 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register mx29f002 flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0~a17 we oe wp reset
4 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b automatic programming the mx29f002t/b is byte programmable using the automatic programming algorithm. the automatic programming algorithm does not require the system to time out or verify the data programmed. the typical chip programming time of the mx29f002t/b at room temperature is less than 3.5 seconds. automatic chip erase typical erasure at room temperature is accomplished in less than 3 seconds. the device is erased using the automatic erase algorithm. the automatic erase algorithm automatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are internally controlled by the device. automatic sector erase the mx29f002t/b is sector(s) erasable using mxic's auto sector erase algorithm. sector erase modes allow sectors of the array to be erased in one erase cycle. the automatic sector erase algorithm automatically programs the specified sector(s) prior to electrical erase. the timing and verification of electrical erase are internally controlled by the device. automatic programming algorithm mxic's automatic programming algorithm requires the user to only write a program set-up commands include 2 unlock write cycle and a0h and a program command (program data and address). the device automatically times the programming pulse width, verifies the program, and counts the number of sequences. a status bit similar to data polling and a status bit toggling between consecutive read cycles, provides feedback to the user as to the status of the programming operation. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. the device will automati- cally pre-program and verify the entire array. then the device automatically times the erase pulse width, verifies the erase, and counts the number of sequences. a status bit similar to data polling and status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. commands are written to the command register using standard microprocessor write timings. register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. during write cycles, the command register internally latches address and data needed for the programming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of we . mxic's flash technology combines years of eprom experience to produce the highest levels of quality, relia- bility, and cost effectiveness. the mx29f002t/b electri- cally erases all bits simultaneously using fowler-nord- heim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection. during a program cycle, the state-machine will control the program sequences and command register will not re- spond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has com- pleted its task, it will allow the command register to respond to its full command set.
5 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data reset 1 xxxh f0h read 1 ra rd read silicon id 4 555h aah 2aah 55h 555h 90h adi ddi sector protect 4 555h aah 2aah 55h 555h 90h (sa) 00h verification (x02h) 01h program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend 1 xxxh b0h sector erase resume 1 xxxh 30h unlock for sector 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 20h protect/unprotect table 1. software command definitions command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 1 defines the valid register command sequences. note: 1. adi = address of device identifier; a1=0,a0 =0 for manufacture code,a1=0, a0 =1 for device code (refer to table 3). ddi = data of device identifier : c2h for manufacture code, 00b0h/0034h for device code. x = x can be vil or vih ra=address of memory location to be read. rd=data to be read at location ra. 2. pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address to the sector to be erased. 3.the system should generate the following address patterns: 555h or 2aah to address a0~a10. address bit a11~a17=x=don't care for all address commands except for program address (pa) and sector address (sa). write sequence may be initiated with a11~a17 in either state. 4.for sector protect verification operation : if read out data is 01h, it means the sector has been protected. if read out dat a is 00h, it means the sector is still not being protected. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. either of the two reset command sequences will reset the device(when applicable).
6 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b pins ce oe we a0 a1 a6 a9 q0~q7 mode read silicon id l l h l l x v id (2) c2h manufacturer code(1) read silicon id l l h h l x v id (2) b0h/34h device code(1) read l l h a0 a1 a6 a9 d out standby h x x x x x x high z output disable l h h x x x x high z write l h l a0 a1 a6 a9 d in (3) sector protect with 12v l v id (2) l x x l v id (2) x system(6) chip unprotect with 12v l v id (2) l x x h v id (2) x system(6) verify sector protect l l h x h x v id (2) code(5) with 12v system sector protect without 12v l h l x x l h x system (6) chip unprotect without 12v l h l x x h h x system (6) verify sector protect/unprotect l l h x h x h code(5) without 12v system (7) reset x x x x x x x high z table 2. mx29f002t/b bus operation notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 1. 2. vid is the silicon-id-read high voltage, 11.5v to 12.5v. 3. refer to table 1 for valid data-in during a write operation. 4. x can be vil or vih. 5. code=00h means unprotected. code=01h means protected. a17~a13=sector address for sector protect. 6. refer to sector protect/unprotect algorithm and waveform. must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12v system" command. 7. the "verify sector protect/unprotect without 12v system" is only following "sector protect/unprotect without 12v system" com- mand.
7 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b read/reset command the read or reset operation is initiated by writing the read/ reset command sequence into the command register. microprocessor read cycles retrieve array data. the device remains enabled for reads until the command register contents are altered. if program-fail or erase-fail happen, the write of f0h will reset the device to abort the operation. a valid command must then be written to place the device in the desired state. silicon-id-read command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacturer and device codes must be accessible while the device resides in the target system. prom programmers typically access signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not generally desired system design practice. the mx29f002t/b contains a silicon-id-read operation to supplement traditional prom programming methodology. the operation is initiated by writing the read silicon id command sequence into the command register. following the command write, a read cycle with a1=vil, a0=vil retrieves the manufacturer code of c2h. a read cycle with a1=vil, a0=vih returns the device code of b0h for mx29f002t, 34h for mx29f002b. pins a0 a1 q7 q6 q5 q4 q3 q2 q1 q0 code(hex) code manufacture code vil vil 11000010c2h device code vih vil 10110000b0h for mx29f002t device code vih vil 0011010034h for mx29f002b sector protection x vih 00000001 01h (protected) verification x vih 00000000 00h (unprotected) table 3. expanded silicon id code set-up automatic chip/sector erase commands chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h. the automatic chip erase does not require the device to be entirely pre-programmed prior to executing the automatic chip erase. upon executing the automatic chip erase, the device will automatically program and verify the entire memory for an all-zero data pattern. when the device is automatically verified to contain an all-zero pattern, a self- timed chip erase and verify begin. the erase and verify operations are completed when the data on q7 is "1" at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verify command is required). if the erase operation was unsuccessful, the data on q5 is "1" (see table 4), indicating the erase operation exceed internal timing limit. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode.
8 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b set-up automatic sector erase commands the automatic sector erase does not require the device to be entirely pre-programmed prior to executing the automatic set-up sector erase command and automatic sector erase command. upon executing the automatic sector erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. the system does not require to provide any control or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verification begin. the erase and verification operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system does not required to provide any control or timing during these operations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). sector erase is a six- bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up command-80h. two more "unlock" write cycles are then followed by the sector erase command-30h. the sector address is latched on the falling edge of we, while the command(data) is latched on the rising edge of we. sector addresses selected are loaded into internal register on the sixth falling edge of we. each successive sector load cycle started by the falling edge of we must begin within 30us from the rising edge of the preceding we. otherwise, the loading period ends and internal auto sector erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase (30h) or erase suspend (boh) during the time-out period resets the device to read mode. erase suspend this command is only valid while the state machine is executing automatic sector erase operation, and therefore will only be responded during automatic sector erase operation. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. after this command has been executed, the command register will initiate erase suspend mode. the state machine will return to read mode automatically after suspend is ready. at this time, state machine only allows the command register to respond to the read memory array, erase resume and program commands. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspended program operation is complete, the system can once again read array data within non- suspended sectors.
9 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b note: 1. q7 and q2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. q5 switches to '1' when an auto program or auto erase operation has exceeded the maximum timing limits. see "q5:exceeded timing limits " for more information. status q7 q6 q5 q3 q2 note1 note2 byte program in auto program algorithm q7 toggle 0 n/a no t oggle auto erase algorithm 0 toggle 0 1 toggle erase suspend read 1 no 0 n/a toggle in progress (erase suspended sector) toggle erase suspended mode erase suspend read data data data data data (non-erase suspended sector) erase suspend program q7 toggle 0 n/a n/a byte program in auto program algorithm q7 toggle 1 n/a no t oggle exceeded auto erase algorithm 0 toggle 1 1 toggle time limits erase suspend program q7 toggle 1 n/a n/a table 4. write operation status
10 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. another erase suspend command can be written after the chip has resumed erasing. set-up automatic program commands to initiate automatic program mode, a three-cycle command sequence is required. there are two "unlock" write cycles. these are followed by writing the automatic program command a0h. once the automatic program command is initiated, the next we pulse causes a transition to an active programming operation. addresses are latched on the falling edge, and data are internally latched on the rising edge of the we pulse. the rising edge of we also begins the programming operation. the system does not require to provide further controls or timings. the device will automatically provide an adequate internally generated program pulse and verify margin. if the program operation was unsuccessful, the data on q5 is "1", indicating the program operation exceed internal timing limit. the automatic programming operation is completed when the data read on q6 stops toggling for two consecutive read cycles and the data on q7 and q6 are equivalent to data written to these two bits, at which time the device returns to the read mode(no program verify command is required). write operation status data polling-q7 the mx29f002t/b also features data polling as a method to indicate to the host system that the automatic program or erase algorithms are either in progress or completed. while the automatic programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to q7. upon completion of the automatic program algorithm an attempt to read the device will produce the true data last written to q7. the data polling feature is valid after the rising edge of the fourth we pulse of the four write pulse sequences for automatic program. while the automatic erase algorithm is in operation, q7 will read "0" until the erase operation is competed. upon completion of the erase operation, the data on q7 will read "1". the data polling feature is valid after the rising edge of the sixth we pulse of six write pulse sequences for automatic chip/sector erase. the data polling feature is active during automatic program/ erase algorithm or sector erase time-out.(see section q3 sector erase timer) q6:toggle bit i the mx29f002t/b features a "toggle bit" as a method to indicate to the host system that the auto program/erase algorithms are either in progress or completed. during an automatic program or erase algorithm operation, successive read cycles to any address cause q6 to toggle. the system may use either oe or ce to control the read cycles. when the operation is complete, q6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, q6 toggles and returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use q6 and q2 together to determine whether a sector is actively erasing or is erase suspended. when the device is actively erasing (that is, the automatic erase algorithm is in progress), q6 toggling. when the device enters the erase suspend mode, q6 stops toggling. however, the system must also use q2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use q7(see the subsection on q7:data polling). if a program address falls within a protected sector, q6 toggles for approximately 2 us after the program command sequence is written, then returns to reading array data. q6 also toggles during the erase-suspend-program mode, and stops toggling once the automatic program algorithm is complete. the write operation status table shows the outputs for toggle bit i on q6. refer to the toggle bit algorithm.
11 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively erasing (that is, the automatic erase algorithm is in process), or whether that sector is erase-suspended. toggle bit i is valid after the rising edge of the final we pulse in the command sequence. q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce to control the read cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 4 to compare outputs for q2 and q6. reading toggle bits q6/ q2 refer to the toggle bit algorithm for the following discussion. whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the q5 exceeded timing limits q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). under these conditions q5 will produce a "1". this time-out condition which indicates that the program or erase cycle was not successfully completed. data polling and toggle bit are the only operating functions of the device under this condition. if this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still functional and may be used for the program or erase operation. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. if this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused). the q5 time-out condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the automatic algorithm operation. hence, the system never reads a valid data on q7 bit and q6 never stops toggling. once the device has exceeded timing limits, the q5 bit will indicate a "1". please note that this is not a device failure condition since the device was incorrectly used. system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of the toggle bit algorithm flow chart).
12 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b q3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. q3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if q3 is low ("0"), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of q3 prior to and following each subsequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. data protection the mx29f002t/b is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. write pulse "glitch" protection noise pulses of less than 5ns(typical) on ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = vil, ce = vih or we = vih. to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected between its vcc and gnd. sector protection with 12v system the mx29f002t/b features hardware sector protection. this feature will disable both program and erase operations for these sectors protected. to activate this mode, the programming equipment must force vid on address pin a9 and control pin oe, (suggest vid = 12v) a6 = vil and ce = vil.(see table 2) programming of the protection circuitry begins on the falling edge of the we pulse and is terminated on the rising edge. please refer to sector protect algorithm and waveform. to verify programming of the protection circuitry, the programming equipment must force vid on address pin a9 ( with ce and oe at vil and we at vih. when a1=1, it will produce a logical "1" code at device output q0 for a protected sector. otherwise the device will produce 00h for the unprotected sector. in this mode, the addresses, except for a1, are in "don't care" state. address locations with a1 = vil are reserved to read manufacturer and device codes.(read silicon id) it is also possible to determine if the sector is protected in the system by writing a read silicon id command. performing a read operation with a1=vih, it will produce a logical "1" at q0 for the protected sector.
13 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b temporary sector unprotect operation (for 29f002t/b only) start reset = vid (note 1) perform erase or program operation reset = vih temporary sector unprotect completed(note 2) 2. all previously protected sectors are protected again. note : operation completed 1. all protected sectors are temporary unprotected. vid=11.5v~12.5v
14 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b temporary sector unprotect parameter std. description test setup all speed options unit tvidr vid rise and fall time (see note) min 500 ns trsp reset setup time for temporary sector unprotect min 4 us note: not 100% tested temporary sector unprotect timing diagram (for 29f002t/b only) reset ce we tvidr tvidr program or erase command sequence 12v 0 or 5v 0 or 5v trsp
15 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b reset timing waveform (for 29f002t/b only) note: not 100% tested ac characteristics parameter std description test setup all speed options unit tready reset pin low (not during automatic algorithms) max 500 ns to read or write (see note) trp1 reset pulse width (during automatic algorithms) min 10 us trp2 reset pulse width (not during automatic algorithms) min 500 ns trh reset high time before read(see note) min 0 ns trh trp2 trp1 tready ce, oe reset reset timing not during automatic algorithms reset timing during automatic algorithms reset
16 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b chip unprotect with 12v system the mx29f002t/b also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. it is recommended to protect all sectors before activating chip unprotect mode. to activate this mode, the programming equipment must force vid on control pin oe and address pin a9. the ce pins must be set at vil. pins a6 must be set to vih.(see table 2) refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. the unprotection mechanism begins on the falling edge of the we pulse and is terminated on the rising edge. it is also possible to determine if the chip is unprotected in the system by writing the read silicon id command. performing a read operation with a1=vih, it will produce 00h at data outputs(q0-q7) for an unprotected sector. it is noted that all sectors are unprotected after the chip unprotect algorithm is completed. sector protection without 12v system the mx29f002t/b also feature a hardware sector protection method in a system without 12v power supply. the programming equipment do not need to supply 12 volts to protect sectors. the details are shown in sector protect algorithm and waveform. chip unprotect without 12v system the mx29f002t/b also feature a hardware chip unprotection method in a system without 12v power supply. the programming equipment do not need to supply 12 volts to unprotect all sectors. the details are shown in chip unprotect algorithm and waveform. power-up sequence the mx29f002t/b powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of a two-step command sequence. vpp and vcc power up sequence is not required. absolute maximum ratings rating value ambient operating temperature 0 o c to 70 o c storage temperature -65 o c to 125 o c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to 7.0v vcc to ground potential -0.5v to 7.0v a9 -0.5v to 13.5v notice: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are subject to change.
17 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b capacitance ta = 25 o c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin1 input capacitance 8 pf vin = 0v cin2 control pin capacitance 12 pf vin = 0v cout output capacitance 12 pf vout = 0v read operation dc characteristics symbol parameter min. typ max. unit conditions ili input leakage current 1(note 3) ua vin = gnd to vcc ilo output leakage current 10 ua vout = gnd to vcc isb1 standby vcc current 1 ma ce = vih isb2 1 5 ua ce = vcc + 0.3v icc1 operating vcc current 30(note 4) ma iout = 0ma, f=5mhz icc2 50 ma iout = 0ma, f=10mhz vil input low voltage -0.3 (note 1) 0.8 v vih input high voltage 2.0 vcc + 0.3 v vol output low voltage 0.45 v iol = 2.1ma voh1 output high voltage(ttl) 2.4 v ioh = -2ma voh2 output high voltage(cmos) vcc-0.4 v ioh = -100ua, vcc=vcc min notes: 1. vil min. = -1.0v for pulse width is equal to or less than 50 ns. vil min. = -2.0v for pulse width is equal to or less than 20 ns. 2. vih max. = vcc + 1.5v for pulse width is equal to or less than 20 ns. if vih is over the specified maximum value, read operation cannot be guaranteed. 3. ili=10ua for industrial grade. 4. icc1=45ma for industrial grade. dc/ac operating conditions for read/programming/erase operation mx29f002/002n -55 -70 -90 -12 operating temperature commercial 0 o c to 70 o c0 o c to 70 o c0 o c to 70 o c0 o c to 70 o c industrial -40 o c to 85 o c -40 o c to 85 o c -40 o c to 85 o c vcc power supply 5v 5% 5v 10% 5v 10% 5v 10%
18 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b ac characteristics 29f002t/b-55 29f002t/b-70 symbol parameter min. max. min. max. unit condition tacc address to output delay 55 70 ns ce=oe=vil tce ce to output delay 55 70 ns oe=vil toe oe to output delay 25 30 ns ce=vil tdf oe high to output float ( note1) 0 20 0 20 ns ce=vil toh address to output hold 0 0 ns ce=oe=vil note: 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. test conditions: input pulse levels: 0.45v/2.4v for 70ns max., 0v/3v for 55ns input rise and fall times: < 10ns for 70ns max. < 5ns for 55ns output load: 1 ttl gate + 100pf (including scope and jig) for 70ns max. 1 ttl gate + 50pf (including scope and jig) for 55ns speed grade reference levels for measuring timing: 0.8v, 2.0v for 70ns max. : 1.5v for 55ns 29f002t/b-90 29f002t/b-12 symbol parameter min. max. min. max. unit conditions tacc address to output delay 90 120 ns ce=oe=vil tce ce to output delay 90 120 ns oe=vil toe oe to output delay 40 50 ns ce=vil tdf oe high to output float ( note1) 0 30 0 30 ns ce=vil toh address to output hold 0 0 ns ce=oe=vil read timing waveforms a0~17 ce oe tacc we vih vil vih vil vih vil vih vil voh vol high z high z data valid toe tdf tce data q0~7 toh add valid
19 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b dc characteristics symbol parameter min. typ max. unit conditions icc1 (read) operating vcc current 30(note 5) ma iout=0ma, f=5mhz icc2 50 ma iou t=0ma, f=10mhz icc3 (program) 50 ma in programming icc4 (erase) 50 ma in erase icces vcc erase suspend current 2 ma ce=vih, erase suspended notes: 1. vil min. = -0.6v for pulse width is equal to or less than 20ns. 2. if vih is over the specified maximum value, programming operation cannot be guaranteed. 3. icces is specified with the device de-selected. if the device is read during erase suspend mode, current draw is the sum of icces and icc1 or icc2. 4. all current are in rms unless otherwise noted. 5. icc1(read)=45ma for industrial grade. command programming/data programming/erase operation
20 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b ac characteristics 29f002t/b-55(note 2) symbol parameter min. max. unit toes oe setup time 0 ns tcwc command programming cycle 70 ns tcep we programming pulse width 45 ns tceph1 we programming pulse width high 20 ns tceph2 we programming pulse width high 20 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 20 ns tdh data hold time 0 ns tcesc ce setup time before command write 0 ns tdf output disable time (note 1) 20 ns taetc total erase time in auto chip erase 3(typ.) 24 s taetb total erase time in auto sector erase 1(typ.) 8 s tavt total programming time in auto verify 7 210 us (byte program time) tbal sector address load time 100 us tch ce hold time 0 ns tcs ce setup to we going low 0 ns tvlht voltage transition time 4 us toesp oe setup time to we active 4 us twpp1 write pulse width for sector protect 10 us twpp2 write pulse width for sector unprotect 12 ms notes: 1. tdf defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. the test conditin of mx29f002t/b-55 : vcc=5v 5%,cl=50pf,vih/vil=3.0v/0v voh/vol=1.5v/1.5v,iol=2ma,ioh=-2ma ta= 0 o c to 70 o c
21 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b ac characteristics 29f002t/b-70 29f002t/b-90 29f002t/b-12 symbol parameter min. max. min. max. min. max. unit toes oe setup time 0 0 0 ns tcwc command programming cycle 70 90 120 ns tcep we programming pulse width 45 45 50 ns tceph1 we programming pulse width high 20 20 20 ns tceph2 we programming pulse width high 20 20 20 ns tas address setup time 0 0 0 ns tah address hold time 45 45 50 ns tds data setup time 30 45 50 ns tdh data hold time 0 0 0 ns tcesc ce setup time before command write 0 0 0 ns tdf output disable time (note 1) 30 40 40 ns taetc total erase time in auto chip erase 3(typ.) 24 3(typ.) 24 3(typ.) 24 s taetb total erase time in auto sector erase 1(typ.) 8 1(typ.) 8 1(typ.) 8 s tavt total programming time in auto verify 7 210 7 210 7 210 us (byte program time) tbal sector address load time 100 100 100 us tch ce hold time 0 0 0 ns tcs ce setup to we going low 0 0 0 ns tvlht voltage transition time 4 4 4 us toesp oe setup time to we active 4 4 4 us twpp1 write pulse width for sector protect 10 10 10 us twpp2 write pulse width for sector unprotect 12 12 12 ms notes: 1. tdf defined as the time at which the output achieves the open circuit condition and data is no longer driven.
22 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b switching test circuits switching test waveforms(i) for speed grade 70ns max. switching test waveforms(ii) for speed grade 55ns(mx29f002t/b-55) 2.0v 2.0v 0.8v 0.8v test points 2.4v 0.45v ac testing: inputs are driven at 2.4v for a logic "1" and 0.45v for a logic "0". input pulse rise and fall times are equal to or less than 20ns. output input 1.5v 1.5v test points 3.0v 0v ac testing: inputs are driven at 3.0v for a logic "1" and 0v for a logic "0". input pulse rise and fall times are < 5ns. output input device under test diodes=in3064 or equivalent cl 1.2k ohm 1.6k ohm +5v cl=100pf including jig capacitance cl=50pf for mx29f002t/b-55
23 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b command write timing waveform add a0~17 ce oe we din tds tah data q0-7 tdh tcs tch tcwc tceph1 tcep toes tas vcc 5v vih vil vih vil vih vil vih vil vih vil add valid
24 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b automatic programming timing waveform automatic programming timing waveform tcwc tas tcep tds tdh tdf vcc 5v ce oe q0~q1,q2 ,q4(note 1) we a11~a17 tceph1 tah add valid tcesc q7 command in add valid a0~a10 command in command in data in data command in command in command in data in data data tavt toe data polling 2aah 555h 555h command #aah command #55h command #a0h (q0~q7) notes: (1). q6:toggle bit, q5:tin=timing-limit bit, q3: time-out bit one byte data is programmed. verify in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. programming completion can be verified by data polling and toggle bit checking after automatic verification starts. device outputs data during programming and data after programming on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform)
25 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes no toggle bit checking q6 not toggled verify byte ok yes q5 = 1 reset auto program completed auto program exceed timing limit no invalid command yes no .
26 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b toggle bit algorithm start read q7~q0 read q7~q0 yes no toggle bit q6 =toggle? q5=1? yes no (note 1) read q7~q0 twice (note 1,2) toggle bit q6 =toggle? program/erase operation not complete, write reset command yes note: 1. read toggle bit q6 twice to determine whether or not it is toggle. see test. 2. recheck toggle bit q6 because it may stop toggling as q5 changes to "1". see test. program/erase operation complete
27 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b all data in chip are erased. external erase verify is not required because data is erased automatically by internal control circuit. erasure completion can be verified by data polling and toggle bit checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) automatic chip erase timing waveform automatic chipe rasetiming waveform tcwc tas tcep tds tdh vcc 5v ce oe q0,q1, q4(note 1) we a11~a17 tceph1 tah q7 command in a0~a10 command in command in command in command in command in taetc data polling 2aah 555h 555h command #aah command #55h command #80h (q0~q7) notes: (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit, q2: toggle bit 555h 2aah 555h command in command in command #aah command in command in command #55h command in command in command #10h
28 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no toggle bit checking q6 not toggled write data 10h address 555h write data 55h address 2aah reset auto chip erase exceed timing limit data polling q7 = 1 yes q5 = 1 auto chip erase completed no . no invalid command yes
29 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b sector data indicated by a13 to a17 are erased. external erase verification is not required because data are erased automatically by internal control circuit. erasure comple- tion can be verified by data polling and toggle bit checking automatic sector erase timing waveform after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) automatic sector erase timing waveform tah sector address0 555h 2aah 2aah 555h 555h sector address1 sector addressn vcc 5v ce oe q0,q1, q4(note 1) we a13~a17 q7 a0~a10 command in command in command in command in command in command in command in command in command in command in command in command in command in command in command #30h command #30h command #30h command #55h command #aah command #80h command #55h command #aah (q0~q7) command in command in tdh tds tcep tcwc taetb tbal data polling tceph1 tas notes: (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit, q2: toggle bit
30 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no toggle bit checking q6 not toggled write data 30h sector address write data 55h address 2aah reset auto sector erase exceed timing limit data polling q7 = 1 q5 = 1 auto sector erase completed load other sector addrss if necessary (load other sector address) yes no last sector to erase time-out bit checking q3=1 ? toggle bit checking q6 toggled ? invalid command no yes yes no yes no
31 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b erase suspend/erase resume flowchart start write data b0h toggle bit checking q6 not toggled yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no . . yes yes no
32 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b timing waveform for sector protection for system with 12v toe data oe we 12v 5v 12v 5v ce a9 a1 a6 toesp twpp 1 tvlht tvlht tvlht verify 01h f0h a17-a13 sector address
33 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b timing waveform for chip unprotection for system with 12v toe data oe we 12v 5v 12v 5v ce a9 a1 toesp twpp 2 tvlht tvlht tvlht verify 00h a6 f0h
34 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b sector protection algorithm for system with 12v start set up sector addr (a17,a16,a15,a14,a13) plscnt=1 sector protection complete data=01h? ye s . oe=vid,a9=vid,ce=vil a6=vil activate we pulse time out 10us set we=vih, ce=oe=vil a9 should remain vid read from sector addr=sa, a1=1 protect another sector? remove vid from a9 write reset command device failed plscnt=32? ye s no no
35 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b chip unprotection algorithm for system with 12v start protect all sectors plscnt=1 chip unprotect complete data=00h? ye s set oe=a9=vid ce=vil,a6=1 activate we pulse time out 12ms set oe=ce=vil a9=vid,a1=1 set up first sector addr all sectors have been verified? remove vid from a9 write reset command device failed plscnt=1000? no increment plscnt no read data from device ye s ye s no increment sector addr * it is recommended before unprotect the whole chip, all sectors should be protected in advance.
36 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b timing waveform for sector protection for system without 12v toe data oe we ce a1 a6 * see the following note! verify 01h a17-a13 sector address 5v note1: must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12v provided. note2: except f0h toggle bit polling don't care (note 2) tcep f0h
37 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b timing waveform for chip unprotection for system without 12v toe data we ce a1 verify 00h a6 note1: must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12v provided. oe tcep 5v toggle bit polling don't care (note 2) * see the following note! f0h note2: except f0h
38 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b sector protection algorithm for system without 12v start set up sector addr (a17,a16,a15,a14,a13) plscnt=1 sector protection complete data=01h? ye s . oe=vih,a9=vih ce=vil,a6=vil activate we pulse to start data don't care set ce=oe=vil a9=vih read from sector addr=sa, a1=1 protect another sector? write reset command device failed plscnt=32? ye s no increment plscnt no write "unlock for sector protect/unprotect" command(table1) toggle bit checking q6 not toggled no ye s ye s no
39 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b chip unprotection algorithm for system without 12v start protect all sectors plscnt=1 chip unprotect complete data=00h? ye s set oe=a9=vih ce=vil,a6=1 activate we pulse to start data don't care set oe=ce=vil a9=vih,a1=1 set up first sector addr all sectors have been verified? write reset command device failed plscnt=1000? no increment plscnt no read data from device ye s ye s no increment sector addr * it is recommended before unprotect the whole chip, all sectors should be protected in advance. write "unlock for sector protect/unprotect" command (table 1) toggle bit checking q6 not toggled ye s no
40 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b id code read timing waveform mode tacc tce tacc toe toh toh tdf data out c2h b0h/34h vid vih vil add a9 add ad add a2-a8 a10-a17 ce oe we a1 data out data q0-q7 vcc 5v vih vil vih vil vih vil vih vil vih vil vih vil
41 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b ordering information plastic package part no. access time operating current standby current temperature package (ns) (ma) max.(ua) range mx29f002tpc-55 55 30 5 0 o c~70 o c 32 pin pdip mx29f002tpc-70 70 30 5 0 o c~70 o c 32 pin pdip mx29f002tpc-90 90 30 5 0 o c~70 o c 32 pin pdip mx29f002tpc-12 120 30 5 0 o c~70 o c 32 pin pdip mx29f002ttc-55 55 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002ttc-70 70 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002ttc-90 90 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002ttc-12 120 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002tqc-55 55 30 5 0 o c~70 o c 32 pin plcc mx29f002tqc-70 70 30 5 0 o c~70 o c 32 pin plcc mx29f002tqc-90 90 30 5 0 o c~70 o c 32 pin plcc mx29f002tqc-12 120 30 5 0 o c~70 o c 32 pin plcc mx29f002bpc-55 55 30 5 0 o c~70 o c 32 pin pdip mx29f002bpc-70 70 30 5 0 o c~70 o c 32 pin pdip mx29f002bpc-90 90 30 5 0 o c~70 o c 32 pin pdip mx29f002bpc-12 120 30 5 0 o c~70 o c 32 pin pdip mx29f002btc-55 55 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002btc-70 70 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002btc-90 90 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002btc-12 120 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002bqc-55 55 30 5 0 o c~70 o c 32 pin plcc mx29f002bqc-70 70 30 5 0 o c~70 o c 32 pin plcc mx29f002bqc-90 90 30 5 0 o c~70 o c 32 pin plcc mx29f002bqc-12 120 30 5 0 o c~70 o c 32 pin plcc mx29f002ntpc-55 55 30 5 0 o c~70 o c 32 pin pdip mx29f002ntpc-70 70 30 5 0 o c~70 o c 32 pin pdip mx29f002ntpc-90 90 30 5 0 o c~70 o c 32 pin pdip mx29f002ntpc-12 120 30 5 0 o c~70 o c 32 pin pdip mx29f002nttc-55 55 30 5 0 o c~70 o c 32 pin tsop (normal type)
42 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b part no. access time operating current standby current temperature package (ns) (ma) max.(ua) range mx29f002nttc-70 70 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002nttc-90 90 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002nttc-12 120 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002ntqc-55 55 30 5 0 o c~70 o c 32 pin plcc mx29f002ntqc-70 70 30 5 0 o c~70 o c 32 pin plcc mx29f002ntqc-90 90 30 5 0 o c~70 o c 32 pin plcc mx29f002ntqc-12 120 30 5 0 o c~70 o c 32 pin plcc mx29f002nbpc-55 55 30 5 0 o c~70 o c 32 pin pdip mx29f002nbpc-70 70 30 5 0 o c~70 o c 32 pin pdip mx29f002nbpc-90 90 30 5 0 o c~70 o c 32 pin pdip mx29f002nbpc-12 120 30 5 0 o c~70 o c 32 pin pdip mx29f002nbtc-55 55 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002nbtc-70 70 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002nbtc-90 90 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002nbtc-12 120 30 5 0 o c~70 o c 32 pin tsop (normal type) mx29f002nbqc-55 55 30 5 0 o c~70 o c 32 pin plcc mx29f002nbqc-70 70 30 5 0 o c~70 o c 32 pin plcc mx29f002nbqc-90 90 30 5 0 o c~70 o c 32 pin plcc mx29f002nbqc-12 120 30 5 0 o c~70 o c 32 pin plcc mx29f002tpi-70 70 45 5 -40 o c~85 o c 32 pin pdip mx29f002tpi-90 90 45 5 -40 o c~85 o c 32 pin pdip mx29f002tpi-12 120 45 5 -40 o c~85 o c 32 pin pdip mx29f002tti-70 70 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002tti-90 90 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002tti-12 120 45 5 -40 o c~85 o c 32 pin tsop (normal type) IMX29F002TQI-70 70 45 5 -40 o c~85 o c 32 pin plcc mx29f002tqi-90 90 45 5 -40 o c~85 o c 32 pin plcc mx29f002tqi-12 120 45 5 -40 o c~85 o c 32 pin plcc imx29f002bpi-70 70 45 5 -40 o c~85 o c 32 pin pdip mx29f002bpi-90 90 45 5 -40 o c~85 o c 32 pin pdip mx29f002bpi-12 120 45 5 -40 o c~85 o c 32 pin pdip
43 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b part no. access time operating current standby current temperature package (ns) (ma) max.(ua) range imx29f002bti-70 70 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002bti-90 90 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002bti-12 120 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002bqi-70 70 45 5 -40 o c~85 o c 32 pin plcc mx29f002bqi-90 90 45 5 -40 o c~85 o c 32 pin plcc mx29f002bqi-12 120 45 5 -40 o c~85 o c 32 pin plcc mx29f002ntpi-70 70 45 5 -40 o c~85 o c 32 pin pdip mx29f002ntpi-90 90 45 5 -40 o c~85 o c 32 pin pdip mx29f002ntpi-12 120 45 5 -40 o c~85 o c 32 pin pdip mx29f002ntti-70 70 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002ntti-90 90 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002ntti-12 120 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002ntqi-70 70 45 5 -40 o c~85 o c 32 pin plcc mx29f002ntqi-90 90 45 5 -40 o c~85 o c 32 pin plcc mx29f002ntqi-12 120 45 5 -40 o c~85 o c 32 pin plcc mx29f002nbpi-70 70 45 5 -40 o c~85 o c 32 pin pdip mx29f002nbpi-90 90 45 5 -40 o c~85 o c 32 pin pdip mx29f002nbpi-12 120 45 5 -40 o c~85 o c 32 pin pdip mx29f002nbti-70 70 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002nbti-90 90 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002nbti-12 120 45 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f002nbqi-70 70 45 5 -40 o c~85 o c 32 pin plcc mx29f002nbqi-90 90 45 5 -40 o c~85 o c 32 pin plcc mx29f002nbqi-12 120 45 5 -40 o c~85 o c 32 pin plcc
44 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b part no. access time operating current standby current temperature package (ns) (ma) max.(ua) range mx29f002ttc-70g 70 30 5 0 o c~70 o c 32 pin tsop (pb-free) mx29f002ttc-90g 90 30 5 0 o c~70 o c 32 pin tsop (pb-free) mx29f002btc-70g 70 30 5 0 o c~70 o c 32 pin tsop (pb-free) mx29f002btc-90g 90 30 5 0 o c~70 o c 32 pin tsop (pb-free) mx29f002tqc-70g 70 30 5 0 o c~70 o c 32 pin plcc (pb-free) mx29f002tqc-90g 90 30 5 0 o c~70 o c 32 pin plcc (pb-free) mx29f002bqc-70g 70 30 5 0 o c~70 o c 32 pin plcc (pb-free) mx29f002bqc-90g 90 30 5 0 o c~70 o c 32 pin plcc (pb-free) mx29f002tpc-70g 70 30 5 0 o c~70 o c 32 pin pdip (pb-free) mx29f002tpc-90g 90 30 5 0 o c~70 o c 32 pin pdip (pb-free) mx29f002bpc-70g 70 30 5 0 o c~70 o c 32 pin pdip (pb-free) mx29f002bpc-90g 90 30 5 0 o c~70 o c 32 pin pdip (pb-free) mx29f002tpi-70g 70 45 5 -40 o c~85 o c 32 pin pdip (pb-free) mx29f002tpi-90g 90 45 5 -40 o c~85 o c 32 pin pdip (pb-free) mx29f002bpi-70g 70 45 5 -40 o c~85 o c 32 pin pdip (pb-free) mx29f002bpi-90g 90 45 5 -40 o c~85 o c 32 pin pdip (pb-free)
45 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b part no. access time operating current standby current temperature package (ns) (ma) max.(ua) range mx29f002nttc-70g 70 30 5 0 o c~70 o c 32 pin tsop (pb-free) mx29f002nttc-90g 90 30 5 0 o c~70 o c 32 pin tsop (pb-free) mx29f002nbtc-70g 70 30 5 0 o c~70 o c 32 pin tsop (pb-free) mx29f002nbtc-90g 90 30 5 0 o c~70 o c 32 pin tsop (pb-free) mx29f002ntqc-70g 70 30 5 0 o c~70 o c 32 pin plcc (pb-free) mx29f002ntqc-90g 90 30 5 0 o c~70 o c 32 pin plcc (pb-free) mx29f002nbqc-70g 70 30 5 0 o c~70 o c 32 pin plcc (pb-free) mx29f002nbqc-90g 90 30 5 0 o c~70 o c 32 pin plcc (pb-free) mx29f002ntpc-70g 70 30 5 0 o c~70 o c 32 pin pdip (pb-free) mx29f002ntpc-90g 90 30 5 0 o c~70 o c 32 pin pdip (pb-free) mx29f002nbpc-70g 70 30 5 0 o c~70 o c 32 pin pdip (pb-free) mx29f002nbpc-90g 90 30 5 0 o c~70 o c 32 pin pdip (pb-free)
46 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time. limits parameter min. typ.(2) max.(3) units sector erase time 1 8 s chip erase time 3 24 s byte programming time 7 210 us chip programming time 3.5 10.5 sec erase/program cycles 100,000 cycles latch-up characteristics erase and programming performance(1) note: 1. not 100% tested, excludes external system level over head. 2.typical values measured at 25 c, 5v. 3.maximum values measured at 25 c, 4.5v. parameter min. unit data retention time 20 years data retention
47 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b package information
48 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b
49 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b
50 rev. 1.5, mar. 28, 2005 p/n: pm0547 mx29f002/002n t/b revision history revision description page date 1.0 1.removed "advanced information" datasheet marking and p1 dec/27/1999 contain information on products in full production 2.the modification summary of revision 0.9.8 to revision 1.0: 2-1.program/erase cycle times:10k cycles-->100k cycles p1,46 2-2.to add data retention 20 years p1,46 2-3.to add industrial grade range from "read mode" to "full range" p17,19,21,41-43 2-4.to remove a9 from "timing waveform for sector protection for p36 system without 12v" to remove a9 from "timing waveform for chip unprotection for p37 system without 12v" 2-5.multi-sector erase time-out:30ms-->30us, tbal:80us-->100us p8,20,21 1.1 modified "package information" p45~47 jun/14/2001 1.2 1. corrected typing error all jun/11/2002 1.3 1. changed part no. from mx29f002/002n to mx29f002/002nt/b all nov/11/2002 1.4 1. added pb-free option for pdip package p43 nov/08/2004 1.5 1. added pb-free option for all commercial-grade package with 70ns & 90ns p44,45 mar/28/2005
mx29f002/002n t/b m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

▲Up To Search▲

Price & Availability of IMX29F002TQI-70

	To Download IMX29F002TQI-70 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .